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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* Two differential 3.3V LVPECL output * Crystal oscillator interface designed for 18pF parallel resonant crystals * Crystal input frequency range: 19.33MHz - 30MHz * Output frequency range: 145MHz - 187.5MHz * VCO frequency range: 580MHz - 750MHz * RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.39ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free compliant packages
GENERAL DESCRIPTION
The ICS843252-04 is a 10Gb/12Gb Ethernet Clock Generator and a member of the HiPerClockSTM HiPerClocks TM family of high perfor mance devices from ICS. The ICS843252-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The ICS843252-04 has excellent phase jitter performance and is packaged in a small 16-pin TSSOP, making it ideal for use in systems with limited board space.
IC S
CONFIGURATION TABLE
Crystal Frequency (MHz) 25 25
WITH
25MHZ CRYSTAL
Inputs VCO Frequency (MHz) 750 625
Feedback Divide 30 25
WITH
N Output Divide 4 4
Output Frequency (MHz) 187.5 156.25
Application 12 Gigabit Ethernet 10 Gigabit Ethernet
CONFIGURATION TABLE
Crystal Frequency (MHz) 20 21.25 24 25.5 30
SELECTABLE CRYSTALS
N Output Divide 4 4 4 4 4 Output Frequency (MHz) 150 159.375 150 159.375 187.5 Application SATA 10 Gigabit Fibre Channel SATA 10 Gigabit Fibre Channel 12 Gigabit Ethernet
Inputs Feedback VCO Frequency Divide (MHz) 30 600 30 25 25 25 637.5 600 637.5 750
BLOCK DIAGRAM
OE nPLL_SEL REF_CLK
Pullup Pulldown
PIN ASSIGNMENT
D Q LE nQ1 Q1 VCCO OE nPLL_SEL VCCO Q0 nQ0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT VEE REF_CLK CLK_SEL VCC VCCA FREQ_SEL
Pulldown
1
1
XTAL_IN
OSC
XTAL_OUT CLK_SEL
Pulldown
0
Phase Detector
VCO
580MHz-750MHz
DIV. N /4
0
Q0 nQ0 Q1 nQ1
ICS843252-04
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
0 = /25 (default) 1 = /30
FREQ_SEL
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843252AG-04 www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Description Differential clock outputs. LVPECL interface levels. Output supply pins. Output enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. Pullup LVCMOS/LVTTL interface levels. Selects between the PLL and reference clock as input to the divider. Pulldown When Low, selects PLL. When High, selects reference clock. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Clock select input. When Low, selects cr ystal inputs. When High, Pulldown selects REF_CLK. LVCMOS/LVTTL interface levels. Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 6 4 Name nQ1, Q1 VCCO OE Power Input Output
5 7, 8 9 10 11 12 13 14
nPLL_SEL Q0, nQ0 FREQ_SEL VCCA VCC CLK_SEL REF_CLK
Input Output Input Power Power Input Input
VEE Power Negative supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT, 15, 16 Input XTAL_OUT is the output. XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, JA 89C/W (0 lfpm)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA ICC ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 60 11 80 Maximum 3.465 3.465 Units V V mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage REF_CLK, C LK _S E L, FREQ_SEL, nPLL_SEL OE REF_CLK, C LK _S E L, FREQ_SEL, nPLL_SEL OE VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIH
Input High Current
IIL
Input Low Current
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum 19.33 Typical Fundamental 30 50 7 1 MHz pF mW Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency 156.25MHz @ Integration Range: 1.875MHz - 20MHz 159.375MHz @ Integration Range: 1.875MHz - 20MHz 187.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 145 0.39 0.38 0.38 TBD 400 Typical Maximum 187.5 Units MHz ps ps ps ps ps %
t jit(O)
RMS Phase Jitter (Random); NOTE 1
tsk(o) tR / tF
Output Skew; NOTE 2, 3 Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Please refer to the Phase Noise Plots following this section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
LVPECL
nQx
Noise Power
VCC, VCCA, VCCO
Qx
SCOPE
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQx
80%
Qx nQy Qy
80% VSW I N G
Clock Outputs
20% tR tF
20%
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nQ0, nQ1 Q0, Q1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843252-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F 10
V CCA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843252-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT: For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843051. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 60mW = 337.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 81.8C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.337W * 81.8C/W = 97.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 16 LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3.
VCC
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Q1
VOUT RL 50 VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843252-04 is: 2210
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843252AG-04
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REV. A JANUARY 25, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843252-04
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 43252A04 43252A04 3252A04L 3252A04L Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS843252AG-04 ICS843252AG-04T ICS843252AG-04LF ICS843252AG-04LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843252AG-04
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REV. A JANUARY 25, 2006

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